1. Field of the Invention
This invention relates to integrated circuits (ICs) comprising a substrate carrying a large number of circuit elements including metal-oxide-metal (MOM) capacitors. More particularly, this invention relates to such ICs having means to reduce damage to the capacitors from the effects of electrostatic discharge (ESD).
2. Prior Art
It is well known that ICs are subject to serious damage or destruction as a result of Electrostatic Discharge (ESD) events. The electrostatic charge associated with the discharge can be developed by any of many sources, such as lightning, friction between insulating bodies such as synthetic fiber clothing, and contact with automated chip handling apparatus. Damage occurs when the ESD voltage is accidentally coupled to one of the circuit terminal points to cause a large pulse of current to flow through some portion of the metal interconnect of the chip to a sensitive circuit element of the IC such as a MOM capacitor. Such capacitors, as formed by certain processes, are especially susceptible to oxide punch through, particularly when the ESD energy presents a very fast transient (e.g., with rise times less than 1 nsec). Such transients can be simulated for test purposes by the so-called Charge Device Model (CDM).
In a co-pending application filed Dec. 14, 1993 by D. Beigel, E. Wolfe and W. Krieger, Ser. No. 166,636, there is disclosed a diode-connected transistor especially suitable for protecting bipolar junctions, thin film resistors and diffused resistors from damage. That protective device establishes a voltage barrier of about 30-35 volts for protecting the IC elements. However, such a relatively high voltage level is not appropriate for protecting MOM capacitors. The present invention provides a two-terminal diode configuration having characteristics more suitable for protecting such capacitors from ESD damage.